There is much interest in improving arrays of TFTs which are used to form the switching elements for flat panel liquid crystal displays. These TFT devices may be fabricated with portions of an amorphous, polycrystalline or microcrystalline semi-conductor film to form the body of the transistor devices.
Hydrogenated amorphous silicon is currently used as the active layer in thin film transistors (TFTs) for active matrix liquid crystal displays. This is because it can be deposited in thin, uniform layers over large areas by plasma enhanced chemical vapour deposition (PECVD). However, due to its amorphous structure, it has a very low carrier mobility, which reduces the switching speed of devices and prevents the use of these transistors in display driver circuitry. Amorphous silicon TFTs are also relatively unstable and are useful for display applications only because the duty cycle is relatively low.
Crystalline silicon is required for the higher speed driver circuitry, which necessitates both a driving circuit panel and a display panel within a display device, with interconnections between these two circuit types.
It has been recognised that microcrystalline silicon may offer a solution to these problems because transistors having microcrystalline silicon as the active layer have improved carrier mobility and yet can still be deposited using a PECVD process. Microcrystalline silicon films deposited in this way consist of small crystals, for example up to 100 nm, embedded within an amorphous matrix. If the crystal grains are large enough, then extended state conduction is enhanced and the mobility increased, approximately by a factor of 10 compared to amorphous silicon layers.
However, deposition by PECVD tends to result in grains being produced with a conical structure. This results in the lower 5-10 nm of material being predominantly amorphous. In a bottom gate TFT structure, the bottom part of the silicon film defines the boundary between the gate insulator and silicon body of the transistor. Therefore, in a bottom gate TFT structure the advantage of the crystalline material is largely lost, whereas top gate TFT structures do exhibit improved mobility and significantly improved stability. These improvements in performance have not been achieved for bottom gate structures for the reasons above.
According to a first aspect of the present invention, there is provided a method of manufacturing a transistor, comprising:
(i) defining a gate conductor over an insulating substrate;
(ii) forming a gate insulator layer over the gate conductor;
(iii) depositing a first microcrystalline silicon layer over the gate insulator layer;
(iv) exposing the microcrystalline silicon layer to a nitrogen plasma, thereby forming silicon nitride, and substantially maintaining the crystalline structure;
(v) repeating steps (iii) and (iv) for a plurality of microcrystalline silicon layers;
(vi) forming a further microcrystalline silicon layer over the exposed layers, the further layer defining the semiconductor body of the transistor; and
(vi) defining a source and drain structure over the transistor body.
This method enables the bottom of the transistor body to have a microcrystalline structure, improving the mobility of the semiconductor layer, even at the interface with the gate insulator layer. The exposed layers which form silicon nitride become part of the gate insulator layer, and there is improved structural matching between the gate insulator layer and the semiconductor transistor body, which layers derive from the same microcrystalline silicon structure.
The microcrystalline silicon layer deposited in steps (iii) and (vi) may be formed by a PECVD process, and the plurality of layers deposited in these steps typically have a combined thickness of between 5 and 25 nm. The individual layers deposited may each have a thickness of between 0.5 and 2 nm.
The exposure in step (iv) is preferably exposure to a dense nitrogen plasma produced by electron cyclotron resonance PECVD.
According to a second aspect of the invention, there is provided a bottom gate thin film transistor comprising:
a gate conductor disposed over an insulating substrate;
a gate insulator layer over the gate conductor;
a silicon nitride layer over the gate insulator layer, the silicon nitride layer having a substantially crystallised structure at the top of the layer, and a substantially amorphous structure at the bottom of the layer;
a microcrystalline silicon layer over the silicon nitride layer which defines the semiconductor body of the transistor; and
a source and drain structure over the transistor body.
The crystal structure within the silicon nitride layer enables the semiconductor body of the transistor to have the desired microcrystalline structure throughout the thickness of the layer, and particularly at the semiconductor/insulator interface.
A thin film transistor active plate for an active matrix liquid crystal display may use transistors of the invention